In an insulated-gate semiconductor device having a trench structure, gate electrodes buried in trenches are led out to a substrate surface in peripheral regions along the four sides of a substrate, and are connected to a gate pad portion through wirings extending on the peripheral regions of the substrate (refer to Patent Document 1, for example).
With reference to a plan view of FIG. 9, a conventional insulated-gate semiconductor device is described while a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is taken as an example.
Referring to FIG. 9, the MOSFET has a surface-mountable structure, for example. A substrate SB constituting a chip is formed by providing an n− type semiconductor layer on an n+ type semiconductor substrate. An element region 520 for a MOSFET having a known structure, for example, a trench structure is disposed in a region inside a chain line of a principal surface of the substrate. The structure of MOSFET transistor cells is the same as the known one, and therefore the illustration and detailed description thereof are omitted. The transistor cells are made by: disposing a p type channel layer on a surface of the substrate SB (n− type semiconductor layer); burying gate electrodes 507 inside trenches which are provided in a lattice shape, for example, to penetrate the p type channel layer; and disposing source regions (not illustrated) around the gate electrodes 507.
A source electrode (not illustrated) connected to the source regions is provided on the substantially entire surface of the element region 520, and a substantially circular source pad portion 527 is provided on the source electrode. Moreover, a substantially circular gate pad portion 528 is provided on the element region 520 with an insulating film interposed therebetween.
The gate electrodes 507 in the element region 520 are connected to a gate lead wiring 508 in the peripheral regions of the substrate SB. The gate lead wiring 508 includes lead portions 508a and a coupling portion 508b. The lead portions 508a are formed by burying polycrystalline silicon in trenches provided in the substrate SB (n− type semiconductor layer), and lead out the gate electrodes 507 to the surface of the substrate SB. The lead portions 508a are spaced from one another, and each extend in a direction orthogonal to the closest side of the substrate SB. The coupling portion 508b is a polycrystalline silicon layer extending on the surface of the substrate SB along each of the sides of the substrate SB in such a way as to be substantially orthogonal to the adjacent lead portions 508a, and connects the multiple lead portions 508a together.
For example, the lead portions 508a are provided at each of the four sides of the substrate SB which are parallel with extending directions of the gate electrodes 507 in the lattice shape in the element region 520. The coupling portion 508b extends substantially annularly in the peripheral regions of the substrate SB while coupling all the lead portions 508a together, and is connected to a protection diode Di provided right under the gate pad portion 528. The gate lead wiring 508 and the protection diode Di are connected to each other through a conductor (resistor) 509 made by doping polycrystalline silicon with a desired impurity. In addition, a gate electrode layer 518 is provided on the gate lead wiring 508. The gate electrode layer 518 is a metal wiring which overlap and is in contact with the gate lead wiring 508, and is connected to the gate pad portion 528.
Patent Document 1: Japanese Patent Application Publication No. 2004-281524